标题: 关于VHDL中Loop State error...loop must terminate within 10,000 iterati [打印本页] 作者: tsx81428 时间: 2024-5-19 20:50 标题: 关于VHDL中Loop State error...loop must terminate within 10,000 iterati 关于VHDL中Loop State error...loop must terminate within 10,000 iterations错误解决方法
首先比力下面两段代码：(使用while循环描述偶校验位产生电路) 代码一：
[code]library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity parity_check isport( datain: in std_logic_vector(7 downto 0); y: out std_logic );end parity_check;architecture rtl of parity_check isbegin process(datain) variable tmp: std_logic:='0'; ;不同点 variable i: integer:= 0; ;不同点 begin while i