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verilog实现十进制正数与ASCII码互转
1.小位宽数实现转ASCII码
1.小整数十进制转BCD码（8421码）
十进制数01234567898421码00000001001000110100010101100111100010012.BCD码（8421码）转ASCII码
8421码0000000100100011010001010110011110001001ASCII码（BIN）110000110001110010110011110100110101110110110111111000111001ASCII码（DEC）48495051525354555657ASCII码（HEX）303132333435363738392.大位宽正整数实现转ASCII码
1.整数数位分割（BCD码）
分离数位有多种方法，除法和比力法，除法理解简单，但是在verilog中占用资源严峻，需要使用到除法IP核，以下采用比力法。
比力法分离数位：- 假设一个数为num=123,使用A，B，C来代替百位，十位和个位。(以下为伪代码)
- 分离百位：
- if(num >=900) A = 9; num = num - 900;
- else if(num >=800) A = 8; num = num - 800;
- else if(num >=700) A = 7; num = num - 700;
- else if(num >=600) A = 6; num = num - 600;
- else if(num >=500) A = 5; num = num - 500;
- else if(num >=400) A = 4; num = num - 400;
- else if(num >=300) A = 3; num = num - 300;
- else if(num >=200) A = 2; num = num - 200;
- else if(num >=100) A = 1; num = num - 100;
- else A = 0; num = num ;
- 分离十位和个位：
- if(num >=90) B = 9; C = num - 90;
- else if(num >=80) B = 8; C = num - 80;
- else if(num >=70) B = 7; C = num - 70;
- else if(num >=60) B = 6; C = num - 60;
- else if(num >=50) B = 5; C = num - 50;
- else if(num >=40) B = 4; C = num - 40;
- else if(num >=30) B = 3; C = num - 30;
- else if(num >=20) B = 2; C = num - 20;
- else if(num >=10) B = 1; C = num - 10;
- else B = 0; C = 0 ;
[code]module dec_ascii16( input clk , input rst , input valid , input [15:0] din ,//MAX = 65535 output rdy , output [39:0] dout); reg [$clog2(9999)-1:0] num0; reg [$clog2(999)-1:0] num1; reg [$clog2(99)-1:0] num2; reg [4*4-1:0] dig0; reg [3*4-1:0] dig1; reg [2*4-1:0] dig2; reg [1*4-1:0] dig3; reg [1*4-1:0] dig4; reg [3:0] valid_d; always @(posedge clk)begin if(rst)begin valid_d |
